A complete analytical potential based solution for a 4H-SiC MOSFET in nanoscale

M K Yadav; K P Pradhan; P K Sahu

doi:10.1088/2043-6262/7/2/025011

1. Introduction

Silicon carbide (SiC) was accidentally discovered in 1890 by E G Acheson, an assistant to Thomas Edison [1]. SiC is a compound semiconductor and is a mixture of silicon and carbon with the chemical formula SiC. Silicon is covalently bonded with carbon. In 4H-SiC, 4H is written in the Ramsdell classification scheme where the number indicates the layer and the letter indicates the Bravais lattice [2]. That means in a 4H-SiC structure four hexagonal layers of SiC are present. SiC exists in a kind of polymorphic crystalline building known as a polytype, e.g. 3C-SiC, 4H-SiC, 6H-SiC [2]. Presently 4H-SiC is usually preferred in power device manufacturing. SiC is a wider band-gap (E_g) material with E_g = 3.3 eV [3] as compared to silicon (E_g = 1.1 eV). Hence SiC has a band-gap three times higher than silicon. Due to its large bandgap, it has higher blocking voltage [3]. SiC is the most rising substrate for power MOSFETs and other power devices due to its high blocking voltage, great operating temperature, and admirable thermal conductivity. 4H-SiC MOSFETs are the power MOSFETs devices that have low switching losses and that can deliver low conduction with high breakdown voltages [4]. At the present time, SiC power MOSFETs with breakdown voltages from 500–1500 V [3] are readily available. SiC devices can also be made to have a much thinner drift layer, and greater doping concentration, i.e. the breakdown area for SiC is 2.4 MV cm⁻¹ compared to silicon that has a breakdown discipline of 0.25 MV cm⁻¹ [3]. That means the breakdown field for silicon is ten times lesser than SiC [4]. Electron mobility (μ) for SiC is 950 cm² V⁻¹s⁻¹ [4] compared to silicon, μ = 1400 cm² V⁻¹ s⁻¹ [5]. This analogy shows that electron mobility for SiC is significantly less as compared to silicon. The continuous shrinkage of the device may require the attainment of excessive packing density and higher efficiency. However, the devaluation of the device dimensions in all forms decreases the performance that increases the high short channel effects. Compressing the bulk MOSFET into a nanometer MOSFET causes compelling challenges and difficulties with the control of the short channel effects [6–8]. According to our knowledge of concern, till now there is no analytical model on hand within the literature for the threshold voltage and surface potential of a nanoscale 4H-SiC MOSFET. The model presents the threshold voltage and surface potential of a nanoscale 4H-SiC MOSFET using the two-dimensional (2D) Poisson equation [9]. The 2D Poission equation may be solved by using the four boundary condition in the SiC region, and analyzing the behaviour of the threshold voltage [9, 10], surface potential, and electric field with varying device parameters like gate oxide thickness (t_ox), 4H-SiC thin layer thickness (t_4H-SiC), channel length (L), and body doping (N_A). The intention is to study a physics centered 2D model for a 4H-SiC MOSFET with the aid of solving the 2D Poisson equation [9]. Note that this model can be utilized as a useful tool for the characterization and design of high-efficiency 4H-SiC nanoscale MOSFETs together with the short channel peculiarities by varying various physical parameters. The validity of the model is checked by matching the model results with the 2D simulation results gathered utilizing T-CAD [11, 12].

2. Two-dimensional structure of a 4H-SiC MOSFET

The structure of the 4H-SiC MOSFET is shown in figure 1. When compared to a silicon MOSFET, the 4H-SiC MOSFET structure is especially helpful for device scaling. In this structure a 4H-SiC epilayer is grown on a silicon substrate. The epilayer is doped with the boron concentration of 1×10¹⁷ cm⁻³ [9]. The phosphorus concentration of 2 × 10²⁰ cm⁻³ [9] is used for source and drain region doping. The silicon dioxide layer is maintained between the gate metal and the 4H-SiC layer and the thickness of the gate oxide layer is t_ox. All the device design parameters with specific values are tabulated in table 1. The compact model will be used for the characterization and design of high-efficiency nanoscale 4H-SiC MOSFETs.

Table 1. List of symbols and their description.

Symbol	Confession	Numeric value
L	channel length	100 nm
E_g,SiC	energy band gap of SiC	3.25 eV
K	Boltzmann constant	1.38 × 10⁻²³
V_T	the thermal voltage	0.026 V
E_g,Si	band gap in Si	1.1 eV
Φ_M	metal gate work function	4.35 eV
q	electron charge	1.6 × 10⁻¹⁹ cm⁻³
N_A	body doping concentration.	1 × 10¹⁷ cm⁻³
N	source and drain doping concentration	2 × 10²⁰ cm⁻³
N_b	substrate concentration	1 × 10¹⁵ cm⁻³
n_Si	intrinsic carrier concentration in silicon	1.45 × 10¹⁰ cm⁻³
ε_Si	dielectric constant of Si	11.7
ε_SiC	dielectric constant of SiC	9.7
ε_ox	gate oxide dielectric constant	20
t_Si	silicon film thickness	100 nm
t_SiC	SiC thin film thickness	30 nm
t_ox	thickness of gate oxide layer	5 nm
Φ_S(x)	surface potential in thin film	unknown
V_GS	gate to source voltage.	0.1 V
V_sub	the substrate bias	0 V
V_DS	drain to source voltage	0.5 V
T	Temperature	300 K

2.1. Surface potential and electric field model

Before access of inversion let us write the 2D Poisson equation in the SiC thin film of a 4H-SiC MOSFET, presented in figure 1 as follows [9, 11, 13]

$\begin{eqnarray}&&\displaystyle \frac{{{\rm{d}}}^{2}\phi (x,y)}{{\rm{d}}{x}^{2}}+\displaystyle \frac{{{\rm{d}}}^{2}\phi (x,y)}{{\rm{d}}{y}^{2}}=\displaystyle \frac{q{N}_{A}}{{\varepsilon }_{{\rm{\text{SiC}}}}}\\ &&\quad \quad \quad \quad \quad {\rm{for}}\;0\leqslant x\leqslant L,0\leqslant y\leqslant {t}_{{\rm{\text{Si}}}{\rm{C}}}.\end{eqnarray} \tag{ 1 }$

The surface potential profile in the SiC film will also be approximated by a parabolic function, as carried out in [9, 11, 13], i.e.

$\begin{eqnarray}\phi (x,y) & = & {\phi }_{{S}}(x)+{b}_{1}(x)y+{b}_{2}(x){y}^{2}\\ & & {\rm{for}}\;0\leqslant x\leqslant L,\quad 0\leqslant y\leqslant {t}_{{\rm{\text{SiC}}}},\end{eqnarray} \tag{ 2 }$

where the coefficients b₁(x) and b₂(x) are functions of variable x. Equation (1) may be solved by using the following four boundary conditions [9, 11, 13]:

(a) At the source side the surface potential is

$\begin{eqnarray}&&\phi (\mathrm{0,\; 0})={\phi }_{{S}}(0)={V}_{b{\rm{i}},{\rm{S}}{\rm{i}}{\rm{C}}},\end{eqnarray} \tag{ 3 }$

with

$\begin{eqnarray}&&{V}_{b{\rm{i}},{\rm{S}}{\rm{i}}{\rm{C}}}=\displaystyle \frac{{E}_{g,{\rm{\text{SiC}}}}}{2q}+{\phi }_{F,{\rm{\text{SiC}}}},\end{eqnarray}$

where ${\phi }_{F,{\rm{S}}{\rm{i}}{\rm{C}}}$ is the Fermi potential in SiC.

(b) At the drain side the surface potential is

$\begin{eqnarray}&&\phi (L,0)={\phi }_{{\rm{S}}}(L)={V}_{b{\rm{i}},{\rm{S}}{i}{\rm{C}}}+{V}_{D{\rm{S}}}.\end{eqnarray} \tag{ 4 }$

(c) Electric field at the interface of the gate oxide and SiC film is continuous, i.e.

$\begin{eqnarray}&&{\left[\displaystyle \frac{{\rm{d}}\phi (x,y)}{{\rm{d}}y}\right]}_{y=0}=\displaystyle \frac{{\varepsilon }_{ox}}{{\varepsilon }_{{\rm{S}}{\rm{i}}{\rm{C}}}}\left(\displaystyle \frac{{\phi }_{{\rm{S}}}(x)-{V}_{G{\rm{S}}}}{{t}_{ox}}\right)\cdot \end{eqnarray} \tag{ 5 }$

(d) The electric field at the interface of SiC and the silicon substrate is

$\begin{eqnarray}&&{\left[\displaystyle \frac{{\rm{d}}\phi (x,y)}{{\rm{d}}y}\right]}_{y={t}_{{\rm{S}}{\rm{i}}{\rm{C}}}}=\displaystyle \frac{{\varepsilon }_{{\rm{S}}{\rm{i}}}}{{\varepsilon }_{{\rm{S}}{\rm{i}}{\rm{C}}}}\left(\displaystyle \frac{{V}_{\mathrm{sub}}-\phi (x,{t}_{{\rm{S}}{\rm{i}}{\rm{C}}})}{{t}_{{\rm{S}}{\rm{i}}}}\right)\cdot \end{eqnarray} \tag{ 6 }$

By using the boundary conditions (5) and (6), we can obtain the coefficients b₁(x) and b₂(x). Then by substituting these coefficients into the expression for ϕ(x, y) and setting y = 0, we obtain

$\begin{eqnarray}&&\displaystyle \frac{{{\rm{d}}}^{2}{\phi }_{S}(x)}{{\rm{d}}{x}^{2}}-\alpha {\phi }_{S}(x)=\beta ,\end{eqnarray} \tag{ 7 }$

where

$\begin{eqnarray}&&\alpha =\displaystyle \frac{2\left(1+\frac{{{\rm{C}}}_{{\rm{o}}{\rm{x}}}}{{{\rm{C}}}_{{\rm{S}}{\rm{i}}}}+\frac{{{\rm{C}}}_{{\rm{o}}{\rm{x}}}}{{{\rm{C}}}_{{\rm{S}}{\rm{i}}{\rm{C}}}}\right)}{{t}_{{\rm{S}}{\rm{i}}{\rm{C}}}^{2}\left(\mathrm{1+2}\frac{{{\rm{C}}}_{{\rm{S}}{\rm{i}}{\rm{C}}}}{{{\rm{C}}}_{{\rm{S}}{\rm{i}}}}\right)},\end{eqnarray} \tag{ 8 }$

$\begin{eqnarray}&&\beta =\displaystyle \frac{q{N}_{A}}{{\xi }_{\mathrm{SiC}}}-\displaystyle \frac{2{V}_{\mathrm{GS}}\left(\displaystyle \frac{{C}_{ox}}{{C}_{Si}}+\displaystyle \frac{{C}_{ox}}{{C}_{\mathrm{SiC}}}\right)}{{t}_{\mathrm{SiC}}^{2}\left(\mathrm{1+2}\displaystyle \frac{{C}_{\mathrm{SiC}}}{{C}_{\mathrm{Si}}}\right)}-\displaystyle \frac{2{V}_{\mathrm{svb}}}{{t}_{\mathrm{SiC}}^{2}\left(\mathrm{1+2}\displaystyle \frac{{C}_{\mathrm{SiC}}}{{C}_{\mathrm{Si}}}\right)},\end{eqnarray} \tag{ 9 }$

where C_ox, C_Si and C_SiC, are the capacitances per unit area for the gate oxide layer, silicon layer and 4H-SiC film, respectively

$\begin{eqnarray}&&{C}_{ox}=\displaystyle \frac{{\varepsilon }_{ox}}{{t}_{ox}},{C}_{Si}=\displaystyle \frac{{\varepsilon }_{Si}}{{t}_{Si}}\;{\rm{and}}\;{C}_{\mathrm{SiC}}=\displaystyle \frac{{\varepsilon }_{\mathrm{SiC}}}{{t}_{\mathrm{SiC}}}\cdot \end{eqnarray}$

The solution of equation (7) must satisfy the boundary conditions

$\begin{eqnarray}&&{\phi }_{S}(0)={\phi }_{bi,\mathrm{SiC}},\end{eqnarray} \tag{ 10 }$

and

$\begin{eqnarray}&&{\phi }_{S}(L)={\phi }_{bi,\mathrm{SiC}}+{V}_{DS}.\end{eqnarray} \tag{ 11 }$

Let us set $\lambda =\sqrt{\alpha }$ and $\sigma =\beta /\alpha .$ The second order inhomogeneous differential equation (7) with a constant coefficient has the following solution

$\begin{eqnarray}&&{\phi }_{S}(x)=A{e}^{\lambda x}+B{e}^{-\lambda x}-\sigma ,\end{eqnarray} \tag{ 12 }$

where

$\begin{eqnarray}&&A=\displaystyle \frac{({V}_{bi,\mathrm{SiC}}+\sigma +{V}_{DS})-({V}_{bi,\mathrm{SiC}}+\sigma ){{\rm{e}}}^{-\lambda L}}{1-{{\rm{e}}}^{-2\lambda L}}{{\rm{e}}}^{-\lambda L},\end{eqnarray} \tag{ 13 }$

$\begin{eqnarray}&&B=-\displaystyle \frac{({V}_{bi,\mathrm{SiC}}+\sigma +{V}_{DS}){{\rm{e}}}^{-\lambda L}-({V}_{bi,\mathrm{SiC}}+\sigma )}{1-{{\rm{e}}}^{-2\lambda L}}\cdot \end{eqnarray} \tag{ 14 }$

2.2. Electric field model

By differentiating equation (12) we obtain the electric field

$\begin{eqnarray}&&{\rm{e}}=\displaystyle \frac{{\rm{d}}{\phi }_{S}(x)}{{\rm{d}}x}=A\lambda {{\rm{e}}}^{\lambda x}-B\lambda {{\rm{e}}}^{-\lambda x}\cdot \end{eqnarray} \tag{ 15 }$

2.3. Threshold voltage model

The threshold voltage model can be obtained by calculating the minima of the surface potential (12). From the condition

$\begin{eqnarray}&&\displaystyle \frac{{\rm{d}}{\phi }_{S}(x)}{{\rm{d}}x}=0\end{eqnarray}$

we obtain

$\begin{eqnarray}&&{\phi }_{S,\mathrm{min}}=2\sqrt{AB}-\sigma .\end{eqnarray} \tag{ 16 }$

The threshold voltage is the minimum value of gate to source voltage (V_GS) at which a channel is established by the gate oxide at the surface of the 4H-SiC MOSFET. Therefore, in a 4H-SiC MOSFET, the threshold voltage is taken to be that value of V_GS for which the surface potential is equal to twice the difference between the intrinsic and extrinsic Fermi level ${\phi }_{F,Si}$ [9, 10, 12–15]:

$\begin{eqnarray}&&{\phi }_{{\rm{S}},\mathrm{min}}=2{\phi }_{F,{\rm{S}}{\rm{i}}{\rm{C}}}={\phi }_{\mathrm{th}}.\end{eqnarray} \tag{ 17 }$

Here ${\phi }_{\mathrm{th}}$ is the value of the surface potential at which the inversion electron charge density in the 4H-SiC device is the same as the doping concentration. As a consequence, the threshold voltage is defined as the value of V_GS at which the minimum surface potential ${\phi }_{S,\mathrm{min}}$ is equal to ${\phi }_{\mathrm{th}}.$ Hence, accordingly, we will assess the value of the threshold voltage by substituting expression (16) into equation (17) and solving for equation (16) by putting the expressions of α, β, λ, σ, A and B

$\begin{eqnarray}&&{V}_{\mathrm{th}}=\displaystyle \frac{-{K}_{2}+\sqrt{{K}_{2}^{2}-4{K}_{1}{K}_{3}}}{2{K}_{1}},\end{eqnarray} \tag{ 18 }$

where

$\begin{eqnarray}&&{K}_{1}={b}^{2}[4(N-{N}^{2})-1],\\ &&{K}_{2}=b\{4(N{V}_{bi,\mathrm{SiC}}+M-2MN)-2{\phi }_{\mathrm{th}}\}\\ &&\quad \quad +2ab\{4(N-{N}^{2})-1\},\\ &&{K}_{3}=a\{4(N{V}_{bi,\mathrm{SiC}}+M-2MN)-2{\phi }_{\mathrm{th}}\}\\ &&\quad \quad -{\phi }_{\mathrm{th}}^{2}-4({M}^{2}-M{V}_{bi,\mathrm{SiC}})+{a}^{2}\{4(N-{N}^{2})-1\},\\ &&M=\displaystyle \frac{1-{{\rm{e}}}^{-\lambda L}{V}_{bi,\mathrm{SiC}}+{V}_{{\rm{d}}S}}{2\;\mathrm{sinh}\;x},\\ &&N=\displaystyle \frac{1-{{\rm{e}}}^{-\lambda L}}{2\;\mathrm{sinh}\;x},\\ &&a=\displaystyle \frac{1}{\alpha }\left\{\displaystyle \frac{q{N}_{A}}{{\varepsilon }_{\mathrm{SiC}}}+\displaystyle \frac{1}{{t}_{\mathrm{SiC}}{\varepsilon }_{\mathrm{SiC}}}\left[{C}_{ox}\left(1+\displaystyle \frac{{C}_{Si}}{2{C}_{\mathrm{SiC}}+{C}_{Si}}\right)\right.\right.\\ &&\quad \quad -\left.\left.{C}_{Si}\left(1-\displaystyle \frac{{C}_{Si}}{2{C}_{\mathrm{SiC}}+{C}_{Si}}\right){V}_{\mathrm{sub}}\right]\right\},\\ &&b=-\displaystyle \frac{1}{\alpha }\displaystyle \frac{{C}_{ox}}{{t}_{\mathrm{SiC}}{\varepsilon }_{\mathrm{SiC}}}\left[1+\displaystyle \frac{{C}_{Si}}{2{C}_{\mathrm{SiC}}+{C}_{Si}}\right]\cdot \end{eqnarray}$

where K₁, K₂, K₃, M, N, a, and b are constants and the expressions are as mentioned above and L being the channel length of the device.

Previously Mishra et al [16] have reported the analytical modeling of the potential profile of an SOI (silicon on insulator) tunnel FET by solving the 2D Laplace's equation, i.e.

$\begin{eqnarray}&&\displaystyle \frac{{{\rm{d}}}^{2}\phi (x,y)}{{\rm{d}}{x}^{2}}+\displaystyle \frac{{{\rm{d}}}^{2}\phi (x,y)}{{\rm{d}}{y}^{2}}=0\cdot \end{eqnarray}$

In their approach the impact of space charge has been neglected because of the light doping profile of the channel. However, this work deals with the 2D Poisson's equation, i.e.

$\begin{eqnarray}&&\displaystyle \frac{{{\rm{d}}}^{2}\phi (x,y)}{{\rm{d}}{x}^{2}}+\displaystyle \frac{{{\rm{d}}}^{2}\phi (x,y)}{{\rm{d}}{y}^{2}}=\displaystyle \frac{q{N}_{A}}{{\varepsilon }_{{\rm{S}}{\rm{iC}}}},\end{eqnarray}$

with consideration of the channel doping profile to evaluate the potential distribution, and the threshold voltage of the 4H-SiC MOSFET. Both the approaches consider the same boundary conditions, except the 4th case where they have calculated the electric flux at the channel and buried oxide interface (refer to equation (7) of [16]) and we have determined the electric flux at the channel/substrate interface as there is an SOI layer (refer to equation (6) of this work).

3. Results and discussion

3.1. Surface potential

To validate the suggested analytical model, the 2D device simulator T-CAD [17] is used for the simulation of the surface potential distribution within the SiC layer and the threshold voltage (V_th) variation and the results are compared with the analytical model. Figure 2 shows the surface potential variation along the channel length for distinct values of drain voltages. It is understood from figure 2 that there is no powerful change in the potential at the source side and a very infinitesimal change at the drain side. As a final result, V_DS has a very small effect on I_D after saturation and it is visible from the figure that there is a negligible shift within the factor of the minimum surface potential regardless of the applied drain bias voltage. For this reason, drain-induced barrier lowering is substantially reduced for the 4H-SiC comparable to silicon. The model results and the simulation results [16] are correlated with each other to prove the accuracy of our suggested analytical model.

**Figure 2.** Graph for surface potential versus channel length for *V_DS* = 0.5 V, *V_DS* = 1.0 V, *V_DS* = 1.5 V and *V_DS* = 2.0 V. The device parameters are used as follows: V_sub = 0 V, *V_GS* = 0.1 V, *N_A* = 1 × 10¹⁷ cm⁻³, N = 2 × 10²⁰ cm⁻³, t_SiC = 30 nm, t_ox = 5 nm, t_Si = 100 nm and ϕ_M = 4.35 eV.
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Figure 3 shows the surface potential variation along the channel for various values of oxide thickness. When the gate oxide thickness increased, the electric field decreased. Therefore, due to the fact that the decrement of electric field impact ionization also reduced, the rate of the generation of carriers was low. So, the controllability of the gate over the channel potential increases and it is less prominent to SCEs. Therefore, oxide thickness cannot be scaled right down to very small values due to the fact that the results of tunneling via the thin oxide and hot-carrier end up prominent.

Figure 4 shows the surface potential variation along the channel for various values of gate voltages. It may be observed from the figure that as the gate voltage increases, there is quite an increment in the height of the barrier at the source side and drain side. Therefore the surface potential increases in the channel region. Consequently, drain induced barrier lowering (DIBL) decreases and the immunity to manage the short channel effects (SCEs) is enhanced.

3.2. Electric field

Figure 5 shows the electric field distribution variation along the channel for distinct values of gate oxide thickness. It may be observed from the figure that at the drain side, with an increase in the gate oxide value, the electric field substantially reduces. Hence, the reduction of the electric field experienced by the carriers in the channel may be understood because of the reduction of the hot-carrier effect.

3.3. Threshold voltage

Figure 6 shows the variation of the threshold voltage along the channel for distinct doping concentration. As proven within the figure, the threshold voltage increases with improved body doping concentration. Hence, the scaling of the device can go to a further extent without any further increase in SCEs by increasing the body doping concentration. The threshold voltage obtained from the model correlates very well with the simulation result.

Figure 7 shows the threshold voltage variation alongside the channel for distinct values of gate oxide thickness. When the gate oxide thickness is diminished, the threshold voltage can also be diminished which is the requirement for a faster device. Therefore, continuous scaling down of the gate oxide thickness offers a rise to faster devices. However, oxide thickness cannot be scaled all the way down to very small values because tunneling via the thin oxide layer and hot-carrier effects becomes prominent. It is clear that there is a close match between the analytical outcome and the 2D simulation outcome.

4. Conclusion

Analytical modelling of the electric field, surface potential and threshold voltage for a 4H-SiC MOSFET is developed based on the 2D physical model. The influence of quite a lot of device parameters like gate length scaling, body doping, SiC thickness, gate oxide thickness on the electric field, the surface potential, and the threshold voltage are analyzed. The results envisioned by the model are compared with the 2D simulations performed by using a commercially available device simulator SentaurusTM. There is a large drop in the threshold voltage with the decrease in channel length. The use of 4H-SiC material instead of silicon increases the device performance regarding reduced short channel effects. The compact model adequately predicts the threshold voltage over a gigantic variety of device parameters and can also be conveniently used to characterize and design the nanoscale 4H-SiC MOSFETs with the desired performance.

A complete analytical potential based solution for a 4H-SiC MOSFET in nanoscale

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Abstract

1. Introduction

2. Two-dimensional structure of a 4H-SiC MOSFET