Impact of structural process variation on junctionless silicon nanotube FET

Conventional single gate planar MOSFET has evolved into multi-gate devices such as FinFETs to deal with the short channel effects [1, 2]. Silicon nanotube field effect transistor (SiNT-FET) is known as the advanced version of the multi-gate structures that was explored in 2012 [3]. Since SiNT-FET has the tubular channel controlled by the inner and outer gates, it gives enhanced performance in terms of excellent channel control compared to the silicon nanowire (SiNW) structure [4]. The tunneling operation is realized on SiNT-FET structure in reference [5]. Junction-less operation is realized on the SiNT-FET structure (JLSiNT-FET) in the literature [6] since junction-less transistor has been appeared as one of the most expectant device due to their better immunity to short channel effects (SCEs) and well-matched process flow with the existing CMOS technologies [7].

In the device manufacturing, the process induced variations are inevitable. There have been many literatures available for process variations on MOSFETs and FinFETs [8–11]. Literatures [12, 13] discuss about the sensitivity of the gate-all-around (GAA) MOSFETs to process variations. Analysis of scalability and process variation on SiNW was explored in [14–16]. Process variation study on the vertical SiNW tunnelling FET was done in [15]. Since the SiNT-FET has excellent scalability over SiNW, the impact of the process variation on conventional junction based SiNT-FET is done in [17]. The tube wall thickness and gate length dependencies on the output parameters of JLSiNT-FET are presented in reference [6]. The important physical parameters, silicon tube ovality and gate oxide thickness also influence the characteristics of the device apart from silicon wall thickness and gate length, and hence an organized study of structural process variation together with the important factors such as, silicon tube ovality, gate oxide thickness for inner and outer gates of JLSiNT-FET is to be studied.

In this paper, we have realized the impact of process variation on six important structural factors such as gate length $\left( {{L}_{G}} \right)$, outer gate oxide thickness $\left( {{T}_{{\rm OX }\_{\rm OUT}}} \right)$, inner gate oxide thickness $\left( {{T}_{{\rm OX }\_{\rm IN}}} \right)$, silicon tube wall thickness for two cases: (i) for constant outer diameter (OD) and (ii) for constant inner diameter (ID), and silicon tube ovality. The performance metrics such as ON current $\left( {{I}_{{\rm ON}}} \right)$, OFF current $\left( {{I}_{{\rm OFF}}} \right)$, Threshold voltage $\left( {{V}_{{\rm TH}}} \right)$ and unity gain cut-off frequency $\left( \,{{f}_{T}} \right)$ are provided. The ranking of the structural factors is done using two level full factorial design of experiments (DOE) method.

The rest of the paper is organized as follows. The device description and calibration are dealt in section 2. Section 3 discusses the sensitivity analysis over a range for different structural factors. The ranking of the structural parameters is done using DOE method in section 4. Finally, conclusions are given in section 5.

To execute the simulations, Sentaurus Structure Editor and Sentaurus Device Simulator from TCAD are used. To do the device simulations, Drift-diffusion transport model is used. Normal field degradation, high field saturation, degradation due to doping, degradation due to interface are taken care in the simulations. Carrier carrier scattering, Doping Dependency model, Philips Unified Mobility model and Lombardi models at interface are included in the simulations. Considering the smaller dimensions of the device, Quantum corrections are also included [18]. Based on ITRS standard for the given technology, 50 Ω resistor is added with source and drain contacts in the electrode section of the simulator during AC analysis.

The device structure and its current-voltage characteristics from [6] are used for the device calibration. JLSiNT-FET device created by TCAD is given in figure 1(a), showing all the regions of the device. JLSiNT-FET with gate oxide and spacer removed i.e. Silicon portion alone is shown in figure 1(b). The schematic vertical cross section of the JLSiNT-FET is given in figure 1(c). The schematic circular cross section of the JLSiNT-FET is given in figure 1(d). JLSiNT-FET device details are given in table 1. The calibrated I_D–V_G characteristics plot is given in figure 2.

Table 1. Device details of JLSiNT-FET.

S. No.	Parameters	Dimensions
1	Gate length	45 nm
2	Tube wall thickness	5 nm
3	Tube outer diameter	32 nm
4	Tube inner diameter	22 nm
5	Oxide thickness	1 nm
6	Drain/source length	15 nm
7	Drain/source wall thickness	15 nm
8	Spacer length	25 nm
9	Doping concentration	$1\times {{10}^{19}}\ {\rm c}{{{\rm m}}^{-3}}$
10	Gate electrode work function	4.68 eV

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The structural parameters of JLSiNT-FET such as ${{L}_{G}}$, ${{T}_{{\rm OX }\_{\rm IN}}}$, ${{T}_{{\rm OX }\_{\rm OUT}}}$, ${{T}_{{\rm SI}}}$ and silicon tube ovality $\left( \phi \right)$ are varied over a range. Using the sensitivity analysis, these above structural parameters impact on ${{I}_{{\rm ON}}}, {{I}_{{\rm OFF}}}$ and unity gain frequency ${{f}_{T}}$ are studied. As already stated in introduction, the ${{T}_{{\rm SI}}}$ can be changed either by changing OD (ID constant), or by changing the ID (OD constant) of the silicon tube.

Sensitivity analysis has been done for one factor at a time with $\pm 10\%$ variations (keeping all other parameters constant). The expression (1) given below is used to compute the sensitivity in which $\Delta y$ is the change in the performance metrics, ${{I}_{{\rm ON}}}, {{I}_{{\rm OFF}}}$ and ${{f}_{T}}$ and $\Delta x$ is the change in the structural factors, ${{L}_{G}}$, ${{T}_{{\rm OX }\_{\rm IN}}}$, ${{T}_{{\rm OX }\_{\rm OUT}}}$, ${{T}_{{\rm SI}\_{\rm IN}}}$, ${{T}_{{\rm SI }\_{\rm OUT}}}$ and $\phi$

$$\begin{align} \newcommand{\e}{{\rm e}} \displaystyle {{S}_{y}}\left( x \right)=\left| \frac{{\Delta y}/{y}\;}{{\Delta x}/{x}\;} \right|.\nonumber \end{align} \tag{ 1 }$$

3.1. Structural factors impact on ${{{I}_{{\rm ON}}},{{I}_{{\rm OFF}}}}$ and ${{{f}_{T}}}$

In this subsection, the impact of structural factors on ${{I}_{{\rm ON}}},{{I}_{{\rm OFF}}}$ and ${{f}_{T}}$ is given. Variation of ${{I}_{{\rm ON}}},{{I}_{{\rm OFF}}}$ and ${{f}_{T}}$ is plotted against ${{L}_{G}}$, ${{T}_{{\rm OX }\_{\rm IN}}}$, ${{T}_{{\rm OX }\_{\rm OUT}}}$, ${{T}_{{\rm SI}}}$, and $\phi$, and are given in figures 3–8. The structural parameters values are given in table 2. Their sensitivities are also calculated in this range as given in expression (1) at various points and sensitivity as a function of ${{L}_{G}}$, ${{T}_{{\rm OX }\_{\rm IN}}}$, ${{T}_{{\rm OX }\_{\rm OUT}}}$, ${{T}_{{\rm SI}}}$, and $\phi$ are plotted in the graphs (figures 3–8).

Table 2. Structural factor values of JLSiNT-FET.

Structural factors	Nominal value	Range
${{L}_{G}}$ (nm)	45	18–100
${{T}_{{\rm SI}}}$ (nm)	5	4–8
${{T}_{{\rm OX }\_{\rm IN}}}$ (nm)	1	1–2
${{T}_{{\rm OX }\_{\rm OUT}}}$ (nm)	1	1–2
Ovality $\left( \phi \right)$ (ratio between major to minor axis)	1	1–1.75

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As ${{L}_{G}}$ decreases ${{I}_{{\rm ON}}}$ is expected to increase which can be confirmed from figure 3(a) as expected. I_ON sensitivity is increased with respect to ${{L}_{G}}$. Figure 3(b) shows the usual ${{I}_{{\rm OFF}}}$ versus ${{L}_{G}}$ characteristics and ${{I}_{{\rm OFF}}}$ sensitivity decreases with respect to ${{L}_{G}}$.

Since JLSINT-FET has two gate oxides (inner and outer), there are two cases: (i) varying ${{T}_{{\rm OX }\_{\rm OUT}}}$ (${{T}_{{\rm OX }\_{\rm IN}}}$ is constant) and (ii) varying ${{T}_{{\rm OX }\_{\rm IN}}}$ (${{T}_{{\rm OX }\_{\rm OUT}}}$ is constant). Figure 4(a) depicts that ${{I}_{{\rm ON}}}$ and its sensitivity as a function of ${{T}_{{\rm OX}}}$. It can be observed from figure 4(a) that ${{I}_{{\rm ON}}}$ decreases when ${{T}_{{\rm OX }\_{\rm IN}}}$ or ${{T}_{{\rm OX }\_{\rm OUT}}}$ is increasing. ${{I}_{{\rm ON}}}$'s sensitivity is also decreased with respect to ${{T}_{{\rm OX }\_{\rm IN}}}$ and ${{T}_{{\rm OX }\_{\rm OUT}}}$. The sensitivity is higher for ${{T}_{{\rm OX }\_{\rm OUT}}}$ and this is due to the rate of decrease in effective gate oxide thickness is more when ${{T}_{{\rm OX }\_{\rm OUT}}}$ is increased compared to ${{T}_{{\rm OX }\_{\rm IN}}}$ [17]. The effective oxide thickness is expressed as follows:

$$\begin{align} \newcommand{\e}{{\rm e}} \displaystyle \begin{array}{@{}llcccccccccccccccccc@{}} & {{T}_{{\rm OX }\_{\rm OUT}}}={{a}_{{\rm OUT}}}\ln \left( {{{b}_{{\rm OUT}}}}/{{{a}_{{\rm OUT}}}}\; \right), \nonumber \\ & {{T}_{{\rm OX }\_{\rm IN}}}={{a}_{{\rm IN}}}\ln \left( {{{b}_{{\rm IN}}}}/{{{a}_{{\rm IN}}}}\; \right), \end{array}\nonumber \end{align} \tag{ 2 }$$

where ${{a}_{{\rm OUT}}}$, ${{b}_{{\rm OUT}}}$, ${{a}_{{\rm IN}}}$ and ${{b}_{{\rm IN}}}$ are as shown in figure 1(d).

Figure 4(b) shows ${{I}_{{\rm OFF}}}$ versus ${{T}_{{\rm OX}}}$ plot along with its sensitivity. It can be observed from figure 4(b) that when ${{T}_{{\rm OX}}}$ increases, the channel control by the gates reduces, and hence, ${{I}_{{\rm OFF}}}$ increases. Figure 5(a) gives ${{f}_{T}}$ versus ${{L}_{G}}$ diagram. ${{f}_{T}}$ decreases when ${{L}_{G}}$ increases. The simulation results go with the ${1}/{{{L}_{G}}}\;$ trend with a coefficient value $\left( {{R}^{2}} \right)$ of 0.98. ${{f}_{T}}$ sensitivity is increasing with respect to ${{L}_{G}}$. Figure 5(b) depicts ${{f}_{T}}$ as a function of ${{T}_{{\rm OX }\_{\rm OUT}}}$ and ${{T}_{{\rm OX }\_{\rm IN}}}$. We can see from figure 5(b) that ${{f}_{T}}$ increases with ${{T}_{{\rm OX }\_{\rm IN}}}$. We can see from JLSiNT-FET structure (figure 1(a)) that the inner gate is covering all drain, channel and source regions and hence the inner associated parasitic is more compared with the outer gate (outer gate of JLSiNT-FET is covering only the channel portion). When increasing the inner gate oxide thickness $\left( {{T}_{{\rm OX }\_{\rm IN}}} \right)$, the parasitic associated to inner gate reduces. We also know that

$$\begin{align} \newcommand{\e}{{\rm e}} \displaystyle {{f}_{T}}={{{g}_{m}}}/{\left( 2\pi {{C}_{gg}} \right)},\nonumber \end{align} \tag{ 3 }$$

where, ${{g}_{m}}$ is the trans-conductance, ${{C}_{gg}}$ is the combination of gate to source capacitance $\left( {{C}_{gs}} \right)$, gate to drain capacitance $\left( {{C}_{gd}} \right)$, and overlap capacitance ${{C}_{ov}}$. When ${{C}_{gg}}$ reduces, ${{f}_{T}}$ increases which can be confirmed with the figure 5(b). From figure 5(b), it can also be noted that ${{f}_{T}}$ is more sensitive to ${{T}_{{\rm OX }\_{\rm IN}}}$ compared to ${{T}_{{\rm OX }\_{\rm OUT}}}$.

As mentioned already, the silicon tube thickness can be changed either by changing OD (for constant ID) or by changing the ID (for constant OD). The silicon tube thickness ${{T}_{{\rm SI}}}$ can be changed either by changing OD (for constant ID) or by changing the ID (for constant OD). Channel width is given as $2\pi R$ for outer channel and $2\pi r$ for inner channel where, $R={OD}/{2}\;$ and $r={ID}/{2}\;$. For constant ID, to increase ${{T}_{{\rm SI}}}$ the OD should be increased and hence the channel width also increases. This results the current to increase for constant ID. For constant OD, to increase ${{T}_{{\rm SI}}}$ the ID should be decreased and hence the channel width decreases. This makes the current to decrease for constant OD. The above statement is true for the absolute values of current and not true for normalized values of current. Figure 6(a) shows that ${{I}_{{\rm ON}}}$ and its sensitivity as a function of ${{T}_{{\rm SI}}}$. From figure 6(a) it can be seen that the normalization current goes up when ${{T}_{{\rm SI}}}$ increases for both constant ID and constant OD cases. ${{I}_{{\rm ON}}}$'s sensitivity is decreased when OD is constant whereas ${{I}_{{\rm ON}}}$'s sensitivity increased when ID is constant. Figure 6(b) shows that ${{I}_{{\rm OFF}}}$ and its sensitivity as a function of ${{T}_{{\rm SI}}}$. When ${{T}_{{\rm SI}}}$ increases leakage cross section increases, and hence, ${{I}_{{\rm OFF}}}$ increases which can be noted from figure 6(b). ${{I}_{{\rm OFF}}}$'s sensitivity also increases with respect to ${{T}_{{\rm SI}}}$.

Figure 7(a) gives the ${{f}_{T}}$ and its sensitivity as a function of ${{T}_{{\rm SI}}}$. It can be seen from figure 7(a) that the ${{f}_{T}}$ and its sensitivity increase with respect to ${{T}_{{\rm SI}}}$ for both constant ID and constant OD cases. It can be observed from figure 7(a) that for increasing the ${{T}_{{\rm SI}}}$ we need to decrease the ID (for constant OD case), results reduction in inner gate area, and hence one can anticipate the ${{I}_{{\rm ON}}}$ to reduce. But this inner gate area reduction reduces the parasitic associated with that and thereby increases ${{f}_{T}}$. To increase the ${{T}_{{\rm SI}}}$, we need to increase the OD (for constant ID case). This will increase the outer gate area, which will increase the ${{g}_{m}}$ and ${{C}_{gg}}$ but ${{g}_{m}}$ takes over ${{f}_{T}}$ to increase.

Normally Silicon tube is intended to be a circular shape but because off the critical fabrication procedures, it will end up with oval shape. To capture that effect in device characteristics, the ovality $(\phi)$ of the silicon tube is also varied here. When ovality is 1, the perfect circular tube shape will occur otherwise the oval shape will occur. Figure 7(b) shows f_T and its sensitivity as a function of $\phi$. It can be noted from figure 7(b) that ${{f}_{T}}$ increases due to an increase in the channel width and small reduction in effective oxide thickness with $\phi$. More sensitivity is observed in larger $\phi$. I_ON and its sensitivity as a function of $\phi$ are depicted in figure 8(a). It can be noted from figure 8(a) that when $\phi$ increases ${{I}_{{\rm ON}}}$ increases due to the channel width increases. When $\phi =1$, the JLSiNT-FET is more sensitive. ${{I}_{{\rm OFF}}}$ versus $\phi$ plot is shown in figure 8(b). When $\phi$ increases, the gate control on the channel reduces and so the ${{I}_{{\rm OFF}}}$ increases (from figure 8(b)).

In this section, the structural factors ranks have been done using a two level factorial DOE method for $\pm 10\%$ deviation from the nominal values (table 2). The performance parameters, ${{I}_{{\rm ON}}},\,{{I}_{{\rm OFF}}}$, threshold voltage $\left( {{V}_{{\rm TH}}} \right)$, sub-threshold swing (SS) and ${{f}_{T}}$, are written as a first order polynomial expression, as a function of input factors, ${{L}_{G}}$, ${{T}_{{\rm OX }\_{\rm IN}}}$, ${{T}_{{\rm OX }\_{\rm OUT}}}$, $\phi$, and ${{T}_{{\rm SI}}}$. The expression (2) shows the example for ${{I}_{{\rm ON}}}$ [17]:

$$\begin{align} \newcommand{\e}{{\rm e}} \displaystyle \begin{array}{@{}cccccccccccccccccccc@{}} & {{I}_{{\rm ON}}}\left( {{L}_{G}},{{T}_{{\rm OX }\_{\rm IN}}},{{T}_{{\rm OX }\_{\rm OUT}}},{\rm OD},{\rm ID},\phi \right)={{\beta }_{0}}+{{\beta }_{{{L}_{G}}}}\times {{L}_{G}}+{{\beta }_{{{T}_{{\rm OX }\_{\rm IN}}}}}\times {{T}_{{\rm OX }\_{\rm IN}}} \nonumber \\ & +{{\beta }_{{{T}_{{\rm OX }\_{\rm OUT}}}}}\times {{T}_{{\rm OX }\_{\rm OUT}}}+{{\beta }_{OD}}\times {\rm OD}+{{\beta }_{{\rm ID}}}\times {\rm ID}+{{\beta }_{\phi }}\phi . \end{array}\nonumber \end{align} \tag{ 4 }$$

Based on the $\beta$ value (coefficient terms), the ranking of structural parameters has been done. Expressions for other performance parameters can also be done similarly. Figure 9 shows the individual structural factors ranks that are computed in the above manner. It can be observed from figure 9 that the OD has occupied the first rank and ID has occupied the last rank on the impact of performance metrics, except for ${{V}_{{\rm TH}}}$. It is observed that ${{T}_{{\rm OX }\_{\rm OUT}}}$ is more sensitive compared to ${{T}_{{\rm OX }\_{\rm IN}}}$ in the case of ${{I}_{{\rm ON}}}$ whereas in the case of ${{f}_{T}}$, it is vice versa.

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Overall sensitivity of structural factors is calculated by adding all the β values. Adding all the β values and arranging them in the descending order, the overall ranking is evaluated and is given in table 3. One can observe that OD is the most sensitive factor and ID is the least sensitive parameter. Table 3 depicts that the OD and ovality occupy the top two ranks. The last two ranks are occupied by L_G and ID.

Table 3. Overall ranking for the structural parameters of SiNT-FET.

Rank	Structural factors
1	OD
2	Ovality
3	${{T}_{{\rm OX }\_{\rm IN}}}$
4	${{T}_{{\rm OX }\_{\rm OUT}}}$
5	${{L}_{G}}$
6	ID

In this paper, we have examined the effect of structural factors, ${{L}_{G}}$, ${{T}_{{\rm OX }\_{\rm IN}}}$, ${{T}_{{\rm OX }\_{\rm OUT}}}$, ${{T}_{{\rm SI}}}$, and silicon tube ovality, on the performance metrics, ${{I}_{{\rm ON}}}$, ${{I}_{{\rm OFF}}}$, $SS$, ${{V}_{{\rm TH}}}$ and ${{f}_{T}}$ of JLSiNT-FET using 3D numerical simulations. The investigation is done by the three ways: (i) varying the structural factors over a range and finding their impact on each of the performance factors; (ii) calculating their sensitivity by performing $\pm 10\%$ deviations at different points over a range; and (iii) individual and overall ranking of structural factors with respect to each performance metric using DOE method. The results in the overall ranking show that the OD is the most sensitive factor whereas the ID is the least sensitive factor. Ovality is the significant factor next to OD.